1. Field of the Invention
The present invention relates to a chip package structure and a method of fabricating the same, and in particular, to a stacked-type chip package structure and a method of fabricating the same.
2. Description of Related Art
In the contemporary information world, consumers continuously pursue electronic apparatuses with higher speed, better quality and more functions. For the product outlook, an electronic apparatus is required to be lighter, thinner, shorter and smaller. To achieve the above-mentioned objectives, many manufacturers introduce the concept of systematization into a circuit design to reduce the number of chips disposed in an electronic product. In addition, in terms of the electronic package technique, in order to adapt with the trend of being lighter, thinner, shorter and smaller, various package design concepts such as a multi-chip module (MCM), a chip scale package (CSP) and a stacked-type multi-chip package structure have also been developed.
FIG. 1 is a schematic cross-sectional view of a conventional fan-in stacked-type chip package structure. As shown by FIG. 1, a stacked-type chip package structure 100 mainly includes a first package structure 110, a second package structure 120, a molding compound 130 and a third package structure 140. The first package structure 110 includes a first substrate 112 and a first chip 114 stacked thereon and electrically connected thereto. The second package structure 120 also includes a second substrate 122 and a second chip 124 stacked thereon and electrically connected thereto. As shown by FIG. 1, the second package structure 120 is disposed upside down on the first package structure 110, and the second substrate 122 is electrically connected to the first substrate 112 through a plurality of bonding wires 150. The molding compound 130 is disposed on the first substrate 112 to encapsulate the first package structure 110 and the second package structure 120. The molding compound 130 has a recess 132 to partially expose the second substrate 122. The third package structure 140 includes a third substrate 142 and a third chip 144 stacked thereon and electrically connected thereto. The third package structure 140 is stacked on the second package structure 120 and electrically connected to the second substrate 122 through a plurality of solder balls 152.
In the stacked-type chip package structure 100, because the back of the second substrate 122 is not coated with solder paste nor has the solder balls implanted thereon in advance for being connected with the solder balls 152 of the third package structure 140. Therefore, in a high temperature reflow process, a desirable good connection between the second substrate 122 and the third substrate 142 is often not obtainable due to the warped substrate, and thus the production yield is decreased.
Furthermore, in the above-mentioned process of fabricating the stacked-type chip package structure 100, to form the molding compound 130 encapsulating the first package structure 110 and the second package structure 120, a special mold is required in the molding process, so as to form the recess 132 on the second substrate 122. However, the size of the recess 132 varies with the size of the third package structure 140. Therefore, when the size of the third package structure 140 is changed, it is required to replace the original mold with a different mold or to modify the original mold, in order to proceed the molding process, so that the recess 132 with the desired size can be formed on the second substrate 122.
However, whether to make a new mold or modify the original mold, the cost for fabricating the stacked-type chip package structure and the process time will be substantially increased. Therefore, how to utilize the same mold to fabricate the molding compound that fits to different chip sizes is a primary problem that needs to be solved urgently.